Crystal, semiconductor element and semiconductor device

ABSTRACT

A crystal that is useful for semiconductor element and a semiconductor element that has enhanced electrical properties are provided. A crystal, including: a corundum structured crystalline oxide, the crystalline oxide including gallium and/or indium, and the crystalline oxide further including a metal of Group 4 of the periodic table. The crystal is used to make a semiconductor element, and the obtained semiconductor element is used to make a semiconductor device such as a power card. Also, the semiconductor element and the semiconductor device are used to make a semiconductor system.

TECHNICAL FIELD

The disclosure is related to a crystal, semiconductor element, and asemiconductor device and/or a semiconductor system using thesemiconductor element that are useful for power devices.

BACKGROUND ART

Gallium oxide (Ga₂O₃) is a transparent semiconductor that has a band gapas wide as 4.8-5.3 eV at room temperature and absorbs almost no visiblelight and ultraviolet light. It is accordingly a promising material foruse in optical and electronic devices and transparent electronicsoperated particularly in a deep ultraviolet region. In recent years,photodetectors, light emitting diodes (LED), and transistors based ongallium oxide (Ga₂O₃) have been developed (refer to Non-PatentLiterature 1).

Gallium oxide (Ga₂O₃) has five crystal structures of α, β, γ, δ, and ε,and generally the most stable structure is β-Ga₂O₃. However, having aβ-gallic structure, β-Ga₂O₃ is not always preferred to be used insemiconductor devices, different from crystal systems generally used inelectronic materials and the like. Growth of a β-Ga₂O₃ thin filmrequires a high substrate temperature and a high degree of vacuum,causing a problem of an increase in manufacturing costs. As described inNPL 2, in β-Ga₂O₃, even a high concentration (e.g.,1×10¹⁹/cm³ or more)dopant (Si) had to be annealed at high temperatures from 800° C. to1100° C. after ion implantation to be used as a donor. In contrast,having a crystal structure same as that of a sapphire substrate alreadysold for general purposes, α-Ga₂O₃ is accordingly preferred to be usedin optical and electronic devices. It further has a band gap wider thanthat of β-Ga₂O₃, and thus is particularly useful for a power device andsemiconductors device using α-Ga₂O₃ as the semiconductor are expected.

Patent Literatures 1 and 2 disclose semiconductor devices that useβ-Ga₂O₃ as a semiconductor and use an electrode, to obtain ohmiccharacteristics compatible with it, with two layers of a Ti layer and anAu layer, three layers of a Ti layer, an Al layer, and an Au layer, orfour layers of a Ti layer, an Al layer, a Ni layer, and an Au layer.

Patent Literature 3 discloses a semiconductor device that uses β-Ga₂O₃as a semiconductor and uses any one of Au, Pt, or a laminate of Ni andAu as an electrode to obtain Schottky characteristics compatible withthe semiconductor.

Unfortunately, application of the electrodes in Patent Literatures 1 to3 to a semiconductor device that uses α-Ga₂O₃ as a semiconductor causesa problem, such as not functioning as a Schottky electrode or an ohmicelectrode, failing to attach the electrode to the film, and impairingsemiconductor properties.

In recent years, in case of using gallium oxide as a semiconductor,Ti/Au are used as an Ohmic electrode (Patent Literature 4 to 8. Whilethis Ohmic electrode has a good adhesion between Ohmic electrode and thesemiconductor, it was not enough satisfactory in view of an Ohmicproperties. Therefore, a semiconductor element using gallium oxide withenhanced Ohmic properties has been desired.

RELATED ART Patent Literature

Patent Literature 1 JP-A-2005-260101

Patent Literature 2 JP-A-2009-81468

Patent Literature 3 JP-A-2013-12760

Patent Literature 4 JP-A-2019-016680

Patent Literature 5 JP-A-2019-036593

Patent Literature 6 JP-A-2019-079984

Patent Literature 7 JP-A-2018-60992

Patent Literature 8 WO2016-13554

Non-Patent Literature

-   Non-Patent Literature 1 Jun Liang Zhao et al, “UV and Visible    Electroluminescence From a Sn:Ga2O3/n+-Si Heterojunction by    Metal-Organic Chemical Vapor Deposition”, IEEE TRANSACTIONS ON    ELECTRON DEVICES, VOL. 58, NO. 5 MAY 2011-   Non-Patent Literature 2 Kohei Sasaki et al, “Si-Ion Implantation    Doping in β-Ga2O3 an d Its Application to Fabrication of    Low-Resistance Ohmic Contacts”, Applied Physics Express 6 (2013)    086502

SUMMARY OF INVENTION Technical Problem

An object of the disclosure is to provide a crystal useful for asemiconductor element, and to provide a semiconductor element withenhanced electrical characteristics.

Solution to Problem

As a result of earnest examination to achieve the above object, theinventors found the following matters. Ti/Au has been used as a knownOhmic electrode, however, there was a problem that Ti is diffused into asemiconductor layer that causes a deterioration of electricalproperties. Also, when a Ti diffusion preventing film such as Ni isprovided between a Ti layer and a Au layer, there was a problem that anoxygen of an oxide semiconductor diffuses in an Ohmic electrode thatcauses a deterioration of electrical properties. The inventors foundthat a crystal including: a corundum structured crystalline oxide, thecrystalline oxide including gallium and/or indium, and the crystallineoxide further including a metal of Group 4 of the periodic table hasenhanced Ohmic characteristics. The inventors also found that thesemiconductor element using the above-mentioned crystal has enhancedelectrical properties. The inventors found that the crystal and thesemiconductor element can solve the above-mentioned problem.

In addition, after learning the above findings, the inventors have madefurther research to reach the present invention.

That is, the present invention relates to the followings.

-   [1] A crystal, including: a corundum structured crystalline oxide,    the crystalline oxide including gallium and/or indium, and the    crystalline oxide further including a metal of Group 4 of the    periodic table.-   [2] The crystal according to [1] above, wherein the metal of Group 4    of the periodic table includes at least a metal selected from    titanium, zirconium and hafnium.-   [3] The crystal according to [1] above, wherein the metal of Group 4    of the periodic table is titanium.-   [4] The crystal according to [1] above, wherein the crystalline    oxide contains gallium.-   [5] The crystal according to [1] above, wherein the crystal has a    shape of a film.-   [6] The crystal according to [1] above, wherein the crystal has an    electrical conductivity.-   [7] A semiconductor element, including: the crystal according to [1]    above.-   [8] A semiconductor element, including: a semiconductor layer; an    electrode that is arranged on the semiconductor layer, the electrode    includes the crystal according to [6] above.-   [9] The semiconductor element according to [8] above, wherein the    semiconductor layer includes a crystalline oxide semiconductor as a    major component.-   [10] The semiconductor element according to [9] above, wherein the    crystalline oxide semiconductor has a corundum structure.-   [11] The semiconductor element according to [9] above, wherein the    crystalline oxide semiconductor contains at least one or more metals    selected from aluminum, gallium and indium.-   [12] The semiconductor element according to [7] above, wherein the    semiconductor element is a vertical device.-   [13] The semiconductor element according to [7] above, wherein the    semiconductor element is a power device.-   [14] A semiconductor device, including: the semiconductor element    according to [7] above; a board; and-   a jointing material, and the semiconductor element that is bonded    with the board by using the jointing material,-   the board is a circuit board or a heat dissipation board.-   [15] The semiconductor device according to [14] above, wherein the    semiconductor device is a power module, an inverter, or a converter.-   [16] The semiconductor device according to [14] above, wherein the    semiconductor device is a power card.-   [17] A semiconductor system, including: the semiconductor element    according to [7] above.

Advantageous Effects

The crystal of the disclosure is useful for a semiconductor device. Thesemiconductor device of the disclosure is excellent in electricalcharacteristics.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional schematic diagram illustrating asemiconductor element according to a preferred embodiment of thedisclosure.

FIG. 2 is a diagram illustrating a preferred embodiment of a method ofthe semiconductor element of FIG. 1.

FIG. 3 is a diagram illustrating a preferred embodiment of a method ofthe semiconductor element of FIG. 1.

FIG. 4 is a diagram illustrating a preferred embodiment of a method ofthe semiconductor element of FIG. 1.

FIG. 5 is a diagram illustrating a preferred embodiment of a method ofthe semiconductor element of FIG. 1.

FIG. 6 is a cross-sectional schematic diagram illustrating asemiconductor element according to a preferred embodiment of thedisclosure.

FIG. 7 is a diagram illustrating the results of I-V measurement in anexample.

FIG. 8 is a diagram illustrating an exterior photograph of asemiconductor element (chip) in an example, and an analysis point of thecross-sectional TEM of FIG. 9.

FIG. 9 is a diagram illustrating a cross-sectional TEM image in anexample.

FIG. 10 is a diagram illustrating a result of TEM-EDS analysis ofα-(Ti_(x)Ga_(1-x))₂O₃ film, 0<X<1) in FIG. 9.

FIG. 11 is a diagram illustrating a result of TEM-EDS analysis ofα-(Ti_(x)Ga_(1-x))₂O₃ film, 0<X<1) in FIG. 9.

FIG. 12 is a schematic diagram illustrating a preferred embodiment of apower supply system.

FIG. 13 is a schematic diagram illustrating a preferred embodiment of asystem device.

FIG. 14 is a schematic diagram illustrating a preferred embodiment of apower supply circuit diagram of the power supply.

FIG. 15 is a schematic diagram illustrating a preferred embodiment of asemiconductor device.

FIG. 16 is a schematic diagram illustrating a preferred embodiment of apower card.

FIG. 17 is a schematic diagram illustrating a multilayer structure thatis a major portion of the semiconductor element according to anembodiment of the disclosure.

FIG. 18 is a cross-sectional view schematically showing an embodiment ofa semiconductor device of the present invention.

DESCRIPTION OF EMBODIMENT

A crystal according to an embodiment of the disclosure including: acorundum structured crystalline oxide, the crystalline oxide includinggallium and/or indium, and the crystalline oxide further including ametal of Group 4 of the periodic table. Examples of the metal of Group 4of the Periodic Table include at least a metal selected from titanium,zirconium and hafnium. According to an embodiment of the disclosure, itis preferable that the metal of Group 4 of the Periodic Table istitanium. According to an embodiment of the disclosure, the crystallineoxide preferably contains gallium. A shape of the crystal is notparticularly limited. According to an embodiment of the disclosure, itis preferred that the crystal has a film-shape. Also, the crystal isusually formed by a crystal-growth. The crystal is electricallyconductive, but may be an insulator. The crystal may be a semiconductorcontaining a dopant, may be a electrical conductor, or may be asemi-insulator. According to an embodiment of the disclosure, thecrystal preferably has an electrical conductivity. According to anembodiment of the disclosure, when the crystal is in a form of a film, athickness (film thickness) of the crystal is not particularly limited.According to an embodiment of the disclosure, the thickness ispreferably equal to or more than 5 nm, more preferably equal to or morethan 10 nm. Such a preferred film thickness enables an improvedelectrical characteristics. The term “major component” herein means thatthe crystalline oxide is preferably contained in the crystal at anatomic ratio of equal to or more than 50% to all the components in thecrystal. According to an embodiment of the disclosure, the crystallineoxide is more preferably contained in the crystal at an atomic ratio ofequal to or more than 70% to all the components in the crystal, morepreferably equal to or more than 90%. According to an embodiment of thedisclosure, the crystalline oxide may be contained in the crystal at anatomic ratio in all the components of the crystal that is 100%.

The crystal may be obtained by, forming a film-shaped oxide of galliumand/or indium and a metal of Group 4 of the periodic table. Thefilm-shaped oxide may be obtained by causing a thermal reaction ofgallium and/or indium and a metal of Group 4 of the periodic table. Amethod of forming the crystal is not particularly limited, and may be aknown method. Examples of the method of forming the crystals include adry method and a wet method. Examples of the dry method includesputtering, vacuum deposition, and CVD. Examples of the wet methodinclude screen printing and die coating. A condition of forming thecrystal is not particularly limited. Usually, a condition isappropriately set, that is capable of causing a thermal reaction underan oxidizing atmosphere from metals.

Hereinafter, a preferred embodiment of the crystal in case of using thecrystal as an Ohmic electrode of the semiconductor element. A preferredembodiment is explained by using a semiconductor element illustrated inFIG. 17. A multilayer structure that is a main portion of thesemiconductor element of FIG. 17 includes a semiconductor layer 101 thatis an oxide semiconductor film, a first metal oxide layer 102 a, asecond metal layer 102 b, and a third metal layer 102 c that areprovided on the semiconductor layer 101. According to an embodiment ofthe disclosure, the crystal is used as the first metal oxide layer 102a.

The oxide semiconductor film (hereinafter, also referred to as“semiconductor layer” or “semiconductor film”) is not particularlylimited as long as the oxide semiconductor film is a semiconductor filmcontaining an oxide. According to an embodiment of the disclosure, theoxide semiconductor film may be preferably a semiconductor filmcontaining a metal oxide, more preferably a semiconductor filmcontaining a crystalline oxide semiconductor, most preferably asemiconductor film containing a crystalline oxide semiconductor as amajor component. According to an embodiment of the disclosure, thecrystalline oxide semiconductor preferably contains one or more metalsselected from a metal of group 9 (for example, cobalt, rhodium andiridium) and a metal of group 13 (for example, aluminum, gallium andindium). According to an embodiment of the disclosure, the crystallineoxide semiconductor more preferably contains at least a metal selectedfrom aluminum, indium, gallium and iridium. Also, according to anembodiment of the disclosure, the crystalline oxide semiconductor mostpreferably contains at least gallium and/or indium. A crystal structureof the crystalline oxide semiconductor is not particularly limited.Examples of the crystal structure of the crystalline oxide semiconductorinclude a corundum structure, a β-gallia structure and a hexagonalstructure (for example, ε-type structure). According to an embodiment ofthe disclosure, the crystalline oxide semiconductor preferably has acorundum structure. Also, according to an embodiment of the disclosure,it is more preferable that the crystalline oxide semiconductor has acorundum structure and a m more preferably a main surface of thecrystalline oxide semiconductor is a m-plane. Such a preferredconfiguration enables to suppress a diffusion of oxygen and to improveelectrical characteristics. Also, the crystalline oxide semiconductormay have an off angle. According to an embodiment of the disclosure, thesemiconductor film preferably includes gallium oxide and/or iridiumoxide, and more preferably include α-Ga₂O₃ and/or α-Ir₂O₃. The term“major component” herein means that the crystalline oxide semiconductoris preferably contained in the semiconductor layer at an atomic ratio ofequal to or more than 50% to all the components in the semiconductorlayer. According to an embodiment of the disclosure, the crystallineoxide semiconductor is more preferably contained in the semiconductorlayer at an atomic ratio of equal to or more than 70% to all thecomponent in the semiconductor layer, further more preferably equal toor more than 90%. According to an embodiment of the disclosure, thecrystalline oxide semiconductor may be contained in the semiconductorlayer at an atomic ratio of 100% to all the components in thesemiconductor layer. A thickness of the semiconductor layer is notparticularly limited. The thickness of the semiconductor layer may beequal to or less than 1 μm. The thickness of the semiconductor layer maybe equal to or more than 1 μm. According to an embodiment of thedisclosure, the thickness of the semiconductor layer is preferably equalto or more than 1 μm, more preferably equal to or more than 10 μm. Asurface area of the semiconductor film is not particularly limited. Thesurface area of the semiconductor film may be equal to or more than 1mm² or more, and may be equal to or less than 1 mm². According to anembodiment of the disclosure, the surface area of the semiconductor filmis preferably in a range of from ² 10 mm² to 300 cm, and more preferablyin a range of from ² of 100 mm² to 100 cm. The semiconductor film ispreferably a single crystal film. The semiconductor film may be apolycrystalline film or a crystalline film containing a polycrystalline.Further, the semiconductor film may be a multilayer film including atleast a first semiconductor layer and a second semiconductor layer. ASchottky electrode may be provided on the first semiconductor layer. Inthis case, in the semiconductor layer may be a multilayer film, inwhich, a first carrier concentration of the first semiconductor layer issmaller than a second carrier concentration of the second semiconductorlayer. Also, in this case, the second semiconductor layer usuallycontains a dopant. The carrier concentration of the semiconductor layermay be appropriately set by adjusting a doping amount.

According to an embodiment of the disclosure, the semiconductor layercontains a dopant. The dopant is not particularly limited and may be aknown dopant. Examples of the dopant include an n-type dopant such astin, germanium, silicon, titanium, zirconium, vanadium and niobium, anda p-type dopant such as magnesium, calcium, and zinc. According to anembodiment of the disclosure, the semiconductor layer preferablycontains the n-type dopant. According to an embodiment of thedisclosure, it is more preferable that the semiconductor layer is then-type oxide semiconductor layer. Further, according to an embodiment ofthe disclosure, the n-type dopant is preferably Sn, Ge or Si. Aconcentration of the dopant in the semiconductor layer is preferablyequal to or more than 0.00001 atomic % in a composition of thesemiconductor layer, more preferably in a range of from 0.00001 atomic %to 20 atomic %, and most preferably in a range of from 0.00001 atomic %to 10 atomic %. More specifically, the concentration of the dopant inthe semiconductor layer may be usually in a range of from 1×10¹⁶ per cm³to 1×10²²/cm³. Further, according to an embodiment of the disclosure,the concentration the dopant in the semiconductor layer may be a lowconcentration of, for example, approximately equal to or less than1×10¹⁷/cm³. Further, according to an embodiment of the disclosure, thedopant may be contained in the semiconductor layer at a highconcentration of, approximately equal to or more than 1×10²⁰/cm³. Aconcentration of a fixed charge of the semiconductor layer is also notparticularly limited. According to an embodiment of the disclosure, theconcentration of the fixed charge of the semiconductor layer ispreferably equal to or less than 1×10 cm³/¹⁷. Such a preferredconfiguration enables to form a depletion layer in the semiconductorlayer more favorably.

The semiconductor layer may be formed by using a known method. Examplesof the method of forming the semiconductor layer include CVD method,MOCVD method, MOVPE method, mist-CVD method, mist-epitaxy method, MBEmethod, HVPE method, pulse-growth method and ALD method. According to anembodiment of the disclosure, the method of forming the semiconductorlayer is preferably a mist CVD method or a mist epitaxy method. In themist CVD method or mist epitaxy method, the semiconductor layer isformed as follows, for example. Atomizing a raw material solution tofloat the droplets (atomization step); carrying the obtained atomizeddroplets with a carrier gas to the substrate after atomization (carryingstep); by causing a thermal reaction of the atomized droplets in avicinity of the substrate to form a semiconductor layer containing acrystalline oxide semiconductor as a major component on the substrate(film forming step).

(Atomization Step)

In the atomization step, the raw material solution is atomized. Themethod of atomizing the raw material solution is not particularlylimited as long as the raw material solution can be atomized, and may bea known method, but in the present invention, an atomization methodusing ultrasonic waves is preferred. The atomized droplets obtainedusing ultrasonic waves are preferably zero in initial velocity and floatin the air, for example, rather than spraying like spray, because it isan atomized droplet (including mist) capable of floating in space andtransported as a gas, it is very suitable because there is no damage dueto collision energy. The droplet size is not particularly limited andmay be a droplet of about several millimeters, but is preferably 50um orless, and more preferably 100 nm to 10 μm.

(Raw Material Solution)

The raw material solution is not particularly limited as long as it canbe atomized and contains a raw material capable of forming asemiconductor film, and may be an inorganic material or an organicmaterial. In the present invention, the raw material is preferably ametal or a metal compound, and more preferably contains 1 or 2 or morekinds of metals selected from aluminum, gallium, indium, iron, chromium,vanadium, titanium, rhodium, nickel, cobalt and iridium.

According to an embodiment of the disclosure, the raw material solutioncontaining the metal, in a form of complex or salt, dissolved ordispersed in an organic solvent or water may be used. Examples of theform of the complex include an acetylacetonate complex, a carbonylcomplex, an ammine complex, a hydride complex. Also, examples of theform of the salt include an organic metal salt (e.g., metal acetate,metal oxalate, metal citrate, etc.), metal sulfide, metal nitrate,phosphorylated metal, metal halide (e.g., metal chloride, metal bromide,metal iodide, etc.).

Further, the raw material solution may contain a hydrohalic acid and/oran oxidant as an additive. Examples of the hydrohalic acid includehydrobromic acid, hydrochloric acid and hydroiodic acid. Examples of theoxidant include hydrogen peroxide (H2O2), sodium peroxide (Na2O2),barium peroxide (BaO2), a peroxide including benzoyl peroxide(C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid,ozone water, and an organic peroxide such as peracetic acid andnitrobenzene.

The raw material solution may contain a dopant. The dopant is notparticularly limited unless it deviates from an object of thedisclosure. Examples of the dopant include an n-type dopant or tin,germanium, silicon, titanium, zirconium, vanadium and niobium. Thedopant concentration in general may be in a range of from approximatelyin a range of from 1×10¹⁶/cm³ to 1×10²²/cm³. The dopant concentrationmay be at a lower concentration of, for example, approximately equal toor less than 1×10¹⁷/cm³. According to an embodiment of the disclosure,the dopant may be contained at a high concentration of, for example,approximately equal to or more than 1×10²⁰/cm³.

A solvent of the raw material solution is not particularly limitedunless it deviates from an object of the present invention, and thesolvent may be an inorganic solvent such as water. The solvent may be anorganic solvent such as alcohol. Also, the solvent may be a mixedsolvent of the inorganic solvent and the organic solvent. According toan embodiment of the disclosure, the solvent preferably includes water.

At a carrying step, the atomized droplets are delivered to the substrateby using a carrier gas. The carrier gas is not particularly limitedunless it deviates from an object of the present invention. Examples ofthe carrier gas include oxygen, ozone, an inert gas such as nitrogen andargon and a reducing gas such as hydrogen gas and a forming gas. Thecarrier gas may include one type of carrier gas. Further, the carriergas may contain one or two or more gasses. Also, a diluted gas (e.g.,10-fold diluted carrier gas) and the like may be further used as asecond carrier gas. The carrier gas may be supplied from one or morelocations. The flow rate of the carrier gas is not particularly limited.A flow rate the carrier gas may be preferably a flow rate that enablesthe carrying step to be a supply rate limiting state. More specifically,the flow rate of the carrier gas is preferably equal to or not more than1 LPM, and more preferably in a range of from 0.1 LPM to 1 LPM.

At a film forming step, a film is formed on the uneven portion by areaction of the atomized droplets. The reaction is not particularlylimited as long as the film is formed from the atomized droplets in thereaction. According to an embodiment of the disclosure, the reaction ispreferably a thermal reaction. The thermal reaction may be a reaction inwhich the atomized droplets react with heat. Reaction conditions and thelike are not particularly limited unless it deviates from an object ofthe present invention. In the film forming step, the thermal reaction isin generally carried out at an evaporation temperature of the solvent ofthe raw material solution or at a higher temperature than theevaporation temperature. The temperature during the thermal reactionshould not be too high, and preferably equal to or less than 650° C. Thetemperature during the thermal reaction is preferably in a range of from300° C. to 650° C. Further, the thermal reaction may be conducted in anyatmosphere unless it deviates from an object of the disclosure. Thethermal reaction may be conducted in a vacuum atmosphere, a non-oxygenatmosphere, a reducing gas atmosphere and an oxygen atmosphere. Inaddition, the thermal reaction may be conducted under any conditionincluding under an atmospheric pressure, under an increased pressure,and under a reduced pressure. According to an embodiment of thedisclosure, the thermal reaction may be preferably conducted under anatmospheric pressure. By conducting the thermal reaction under anatmospheric pressure, a calculation of an evaporation temperature wouldbe easier and an equipment and the like would be more simplified.Further, a film thickness of the crystalline oxide semiconductor can beset by adjusting a deposition time

The base is not particularly limited as long as the base can support thesemiconductor film. A material of the base is not particularly limitedunless it deviates from an object of the disclosure, and may be a knownbase. The base may be an organic compound or an inorganic compound. Thebase may be in any shape, and can perform for any shape. Examples of theshape of the base include plate such as flat plate or a disc, fibrous,bar, columnar, prismatic, cylindrical, spiral, spherical and annular.According to one or more embodiments of the disclosure, the base ispreferably a substrate. A thickness of the substrate is not particularlylimited according to one or more embodiments of the disclosure.

The substrate is not particularly limited as long as the substrate is inthe shape of plate and can support the semiconductor film. The substratemay be an insulator substrate, a semiconductor substrate, a metalsubstrate or a conductive substrate, however, the substrate ispreferably an insulator substrate and also preferably a substrate havinga metal film on a surface thereof. Examples of the substrate include asubstrate including a substrate material with a corundum structure as amajor component, a substrate including a substrate material with aβ-Gallia structure as a major component or a substrate including asubstrate material with a hexagonal structure as a major component. Theterm “major component” herein means that the substrate preferablycontains a substrate material with a particular crystalline structure atan atomic ratio of 50% or more to all components of a substrate materialcontained in the substrate. The substrate preferably contains thesubstrate material with the particular crystalline structure at anatomic ratio of 70% or more to all components of the substrate materialcontained in the substrate and more preferably contains at an atomicratio of 90% or more. The substrate may contain the substrate materialwith the particular crystalline structure at an atomic ratio of 100% toall components of the substrate material contained in the substrate.

Furthermore, a material for the substrate is not particularly limited ifan object of the present inventive subject matter is not interferedwith, and also, the material may be a known one. Examples of a substratewith a corundum structure include α-Al₂O₃ (sapphire substrate) andα-Ga₂O₃. Also, according to an embodiment of the present inventivesubject matter, the substrate may be an a-plane sapphire substrate, anm-plane sapphire substrate, an r-plane sapphire substrate, a c-planesapphire substrate, an α gallium oxide substrate (a-plane, m-plane, orr-plane), and the like. Furthermore, examples of the substrate contain asubstrate material with a P-gallia structure as a major componentinclude a β-Ga₂O₃ substrate, a mixed crystal substrate containing Ga₂O₃and Al₂O₃, where Al₂O₃ is more than 0 wt % and 60 wt % or less, and thelike. Examples of the substrate containing the substrate material with ahexagonal structure as a major component include an SiC substrate, a ZnOsubstrate, a GaN substrate, and the like.

According to an embodiment of the present inventive subject matter,after the film formation process, annealing may be performed. Theannealing temperature may not be particularly limited if an object ofthe present inventive subject matter is not interfered with. Theannealing temperature may be generally from 300° C. to 650° C. Accordingto an embodiment of the present inventive subject matter, the annealingtemperature may be preferably from 350° C. to 550° C. Also, theannealing time is generally from 1 minute to 48 hours. According to anembodiment of the present inventive subject matter, the annealing timemay be preferably from 10 minutes to 24 hours, and further preferablyfrom 30 minutes to 12 hours. The annealing may be performed in anyatmosphere if an object of the present inventive subject matter is notinterfered with. The annealing may be performed in a non-oxygenatmosphere. Also, the annealing may be performed in a nitrogenatmosphere.

According to an embodiment of the disclosure, the semiconductor layermay be provided directly on a base or may be provided on another layer,such as a buffer layer and a stress relief layer, positioned above orbelow the base.

According to an embodiment of the disclosure, a semiconductor layer mayinclude a base, which may be used in a semiconductor device.

The Ohmic electrode includes at least a first metal oxide layer thatforms an Ohmic contact with the semiconductor layer, a second metallayer, and a third metal layer. The second metal layer and the thirdmetal layer are composed of one or more metals that are different fromeach other. The second metal layer is arranged between the first metaloxide layer and the third metal layer. According to an embodiment of thedisclosure, it is preferable that the first metal oxide layer of theOhmic electrode is the crystal. A material of the second metal layerand/or the third metal layer of the Ohmic electrode is not particularlylimited, and may be a known material, respectively. Examples of thesecond metal layer and/or the third metal layer include at least onemetal selected from Groups 4 to 11 of the Periodic Table. Examples of ametal of Group 4 of the Periodic Table include titanium (Ti), zirconium(Zr) and hafnium (Hf). Examples of a metal of Group 5 of the PeriodicTable include vanadium (V), niobium (Nb) and tantalum (Ta). Examples ofmetals of Group 6 of the Periodic Table include chromium (Cr),molybdenum (Mo) and tungsten (W). Examples of a metal of Group 7 of thePeriodic Table include manganese (Mn), technetium (Tc), and rhenium(Re). Examples of a metal of Group 8 of the Periodic Table include iron(Fe), ruthenium (Ru), and osmium (Os). Examples of a metal of Group 9 ofthe Periodic Table include cobalt (Co), rhodium (Rh), and iridium (Ir).Examples of a metal of Group 10 of the Periodic Table include nickel(Ni), palladium (Pd), and platinum (Pt). Examples of a metal of Group 11of the periodic table include copper (Cu), silver (Ag), and gold (Au).According to an embodiment of the disclosure, the second metal layer ispreferably a metal of Group 4 of the Periodic Table, and more preferablytitanium. Further, the third metal layer is preferably a metal of Group10 of the Periodic Table, and more preferably nickel. Such a preferredmetal enables to further improve the electrical characteristics of thecrystal. A thickness of the second metal layer and/or the third metallayer of the ohmic electrode is not particularly limited. The thicknessof each of the second metal layer and/or the third metal layer of theohmic electrode is preferably in a range of from 0.1 nm to 10 μm, andmore preferably in a range of from 1 nm to 1000 nm.

A method of forming the Ohmic electrode is not particularly limited, andmay be a known method. Examples of the method of forming the Ohmicelectrode include a dry method and a wet method. Examples of the dryingmethod include sputtering, vacuum deposition, and CVD. Examples of thewet method include screen printing and die coating. According to anembodiment of the disclosure, the method of forming the crystal ispreferably mist CVD method or mist epitaxy method.

The semiconductor element may include a Schottky electrode. According toa preferred embodiment of the disclosure, the semiconductor element ispreferably a Schottky barrier diode. The Schottky electrode(hereinafter, also referred to as “electrode layer”) is not particularlylimited if the Schottky electrode has a electrical conductivity and canbe used as a Schottky electrode. A material of the electrode layer maybe an electrically conductive inorganic material or may be anelectrically conductive organic material. According to an embodiment ofthe disclosure, the material of the electrode layer is preferably ametal. Examples of a preferred metal include at least one metal selectedfrom Groups 4 to 10 of the Periodic Table. According to an embodiment ofthe disclosure, the electrode layer preferably contains at least onemetal selected from groups 4, group 6 and group 9 of the periodic table.According to an embodiment of the disclosure, the electrode layer morepreferably contains at least one metal selected from Group 6 and 9 ofthe periodic table, and most preferably contains Mo and/or Co. Athickness of the electrode layer is not particularly limited. Accordingto an embodiment of the disclosure, the thickness of the electrode layeris preferably in a range of from 0.1 nm to 10 μm, more preferably in arange of from 5 nm to 500 nm, and most preferably in a range of from 10nm to 200 nm. In addition, According to an embodiment of the disclosure,it is preferable that the electrode layer is made of two or more layersthat have different compositions from each other. Such a preferredconfiguration of the electrode layer enables to obtain a semiconductorelement having enhanced Schottky characteristics and enables to exhibita better effect of a suppression of leakage current.

In case that the first electrode layer includes two or more layersincluding the first electrode layer and the second electrode layer, itis preferable that the second electrode layer has electricalconductivity and has a higher electrical conductivity than the firstelectrode layer. A material of the second electrode layer may be anelectrically conductive inorganic material or an electrically conductiveorganic material. According to an embodiment of the disclosure, thematerial of the second electrode is preferably a metal. Preferableexamples of the metal include at least a metal selected from Groups 8 to13 of the Periodic Table. Examples of the metal of groups 8 to 10 of theperiodic table include the metals of groups 8 to 10 of the periodictable as explained in the description of the metal of the electrodelayer. Examples of the metal of Group 11 of the periodic table includecopper (Cu), silver (Ag), and gold (Au). Examples of metal of group 12of the periodic table include zinc (Zn), and cadmium (Cd). Examples ofthe metal of group 13 of the Periodic Table include aluminum (Al),gallium (Ga), and indium (In). According to an embodiment of thedisclosure, the second electrode layer preferably contains at least onemetal selected from Group 11 and Group 13 of the Periodic Table, andmore preferably contains at least one metal selected from silver,copper, gold and aluminum. A thickness of the second electrode layer isnot particularly limited. The thickness of the second electrode layer ispreferably in a range of from 1 nm to 500 μm, more preferably in a rangeof from 10 nm to 100 μm, and most preferably in a range of from 0. μm to10 μm. According to an embodiment of the disclosure, it is preferablethat a thickness of the insulator film under an outer end of theelectrode layer is thicker than a thickness of the insulator filmpositioned from the opening to a distance of 1 μm from the opening. Sucha preferred configuration enables to have more enhanced breakdownvoltage characteristics of the semiconductor element.

According to a preferred embodiment of the disclosure, the Schottkyelectrode includes a first metal layer, a second metal layer and a thirdmetal layer. Also, according the preferred embodiment of the disclosure,the first metal layer, the second metal layer and the third metal layerincludes metals that are different from each other. The second metallayer is arranged between the first metal layer and the third metallayer. The first metal layer is placed so as to be nearer to thesemiconductor layer side than the third metal layer. In case that theSchottky electrode includes a first metal layer, a second metal layerand a third metal layer, it is preferable that the first metal layerincludes a metal of group 6 of the periodic table or a metal of group 9of the periodic table. Also in this case, it is preferable that thesecond electrode layer includes a metal of group 4 of the periodic tableand the third metal layer includes a metal of group 13 of the periodictable. Here, it is more preferable that the first metal layer is a Colayer or a Mo layer, the second metal layer is a Ti layer, and the thirdmetal layer is an Al layer, respectively.

A method of forming the electrode layer is not particularly limited, andmay be a known method. Examples of the method of forming the Ohmicelectrode include a dry method and a wet method. Examples of the dryingmethod include sputtering, vacuum deposition, and CVD. Examples of thewet method include screen printing and die coating. According to anembodiment of the disclosure, the method of forming the crystal ispreferably mist CVD method or mist epitaxy method.

Further, according to an embodiment of the disclosure, the Schottkyelectrode preferably has a structure in which a thickness is reducingtoward a outer portion of the semiconductor element. In this case, theSchottky electrode may have a tapered region on the side surface.Further, the Schottky electrode may include two or more layers includinga first electrode layer and a second electrode layer, and the outer endof the first electrode layer may be located outer than the outer end ofthe second electrode layer. According to an embodiment of thedisclosure, if the Schottky electrode has a tapered region, the taperangle the tapered region is not particularly limited unless it deviatesfrom an object of the disclosure. The taper angle is preferably equal toor less than 80°, more preferably equal to or less than 60°, and mostpreferably equal to or less than 40°. A lower limit of the taper angleis not particularly limited. The lower limit of the taper angle ispreferably 0.2°, more preferably, 1°. Further, according to anembodiment of the disclosure, in case that the outer end of the firstelectrode layer of the Schottky electrode is positioned outer side thanthe outer end of the second electrode layer, it is preferable that thedistance between the outer end of the first electrode layer and theouter end of the second electrode layer is equal to or more than 1 μm.Such a preferred configuration enables a smaller leakage current.According to an embodiment of the disclosure, it is preferable that atleast a part of a portion of the first electrode layer that ispositioned outer side than the outer end of the second electrode(hereinafter, also referred to as “overhanging portion”) has a structurein which a thickness is reducing toward a outer portion of thesemiconductor element. With such a preferred configuration, it ispossible to further improve a withstand voltage of the semiconductorelement. Also, by using such preferred electrode and above-mentionedpreferred material of the semiconductor layer in combination, it ispossible to obtain the semiconductor element with a lower leakagecurrent and a lower loss.

The semiconductor element preferably includes an oxide semiconductorlayer, and a dielectric film covering at least a side surface of theoxide semiconductor layer. With this configuration, it is possible tosuppress deterioration of semiconductor properties of the oxidesemiconductor film due to a moisture absorption or oxygen in the air.According to an embodiment of the disclosure, the tapered region of theside surface of the semiconductor layer enables not only to improve anadhesion between the semiconductor layer and the dielectric film butalso to improve a stress relaxation that leads a enhanced reliability.

The dielectric film is formed on the semiconductor layer and usually hasan opening. A relative dielectric constant of the dielectric film is notparticularly limited. The dielectric film may be a known dielectricfilm. According to an embodiment of the disclosure, it is preferablethat the dielectric film is formed at least 1 μm or more from theopening. Also, according to an embodiment of the disclosure, it ispreferable that the relative dielectric constant of the dielectric filmis equal to or less than 5. The term “relative dielectric constant”herein means a ratio of the dielectric constant of a film to adielectric constant of vacuum. According to an embodiment of thedisclosure, it is preferable that the dielectric film is a filmcontaining Si. Preferred examples of the film containing Si include asilicon oxide-based film. Examples of the silicon oxide-based filmincludes a SiO₂ film, a phosphorus-doped SiO BPSG film, a boron-dopedSiO₂ film, a phosphorus-doped SiOC film, a SiOF film, and the like. Amethod of forming the dielectric film is not particularly limited.Examples of the method of forming the dielectric film includes CVDmethod, atmospheric pressure CVD method, plasma CVD method, mist CVDmethod, and thermal oxidation method. According to an embodiment of thedisclosure, the method of forming the dielectric film is preferably amist CVD method or atmospheric pressure CVD method.

Also, the semiconductor element according to an embodiment of thedisclosure further includes a porous layer that is arranged on the thirdmetal layer of the Ohmic electrode. The porous layer is not particularlylimited. The porous layer preferably has electrical conductivity, andmore preferably contains a noble metal. According to an embodiment ofthe disclosure, a porosity of the porous layer is preferably equal to orless than 10%. Such a preferred porosity enables to alleviate a warpageor a concentration of thermal stress without impairing semiconductorproperties. A method of forming the porous layer with a porosity that isequal to or less than 10% is not particularly limited, and may be aknown method. According to an embodiment of the disclosure, the porouslayer with a porosity that is equal to or less than 10% may be formed byappropriately setting a sintering conditions such as sintering time,sintering pressure, and a sintering temperature. Examples of the methodof forming the porous layer includes a method in which the porosity isadjusted to be equal to or less than 10% by a crimping under heating(thermocompression bonding). Also, examples of the method of forming aporous layer include a method in which sintering is performed at alonger time than usual. By using such a porous layer having a porosityof equal to or less than 10% in the semiconductor element, it ispossible to to alleviate a warpage or a concentration of thermal stresswithout impairing semiconductor properties. The term “porosity” hereinmeans a ratio of a volume of voids to a volume of the porous layer(including the volume of the voids). The porosity of the porous layermay be determined, for example, based on cross-sectional photographstaken by using scanning electron microscopy (SEM: Scanning ElectronMicroscope). More specifically, the porosity of the porous layer may bedetermined by following steps. A cross-sectional photograph of theporous layer (SEM image) is taken at a plurality of positions. Next,using a commercially available image analysis software, performingbinarization of a captured SEM image to obtain a ratio of a portioncorresponding to the void (for example, a black portion) in the SEMimage. The ratio of the black portion obtained from the SEM image takenat a plurality of positions is averaged to determine the porosity of theporous layer. The term “porous layer” herein includes not only a porousfilm that has a continuous film-shape, but also a porous film withaggregate shape.

Also, according to an embodiment of the disclosure, it is preferablethat a substrate is arranged on the porous layer. The substrate may bedirectly arranged on the porous layer. The substrate may be arranged onthe porous layer via other layers including one or more metal layers(for example, the above-mentioned metal layers).

A direction of current flow of the semiconductor element according to anembodiment of the disclosure is not particularly limited. According toan embodiment of the disclosure, it is preferable that the Schottkyelectrode is arranged on a first surface side of the oxide semiconductorfilm and the Ohmic electrode is arranged on a second surface side of theoxide semiconductor film that is opposite to the first surface side.According to an embodiment of the disclosure, it is more preferable thatthe semiconductor element is a vertical device.

EXAMPLE

Hereinafter, preferred embodiments of the disclosure will be describedin more detail with reference to drawings. The disclosure is not limitedto the following embodiments.

FIG. 1 illustrates a main portion of a Schottky barrier diode (SBD) thatis a semiconductor element according to a preferable embodiment of thedisclosure. The SBD of FIG. 1 includes an Ohmic electrode 102, asemiconductor layer 101, a Schottky electrode 103, and a dielectric film104. The ohmic electrode 102 includes a metal oxide layer (crystal) 102a, a metal layer 102 b, and a metal layer 102 c. The semiconductor layer101 includes a first semiconductor layer 101 a and a secondsemiconductor layer 101 b. The Schottky electrode 103 includes a metallayer 103 a, a metal layer 103 b, and a metal layer 103 c. The firstsemiconductor layer 101 a is, for example, an n −-type semiconductorlayer. The second semiconductor layer 101 b is, for example, an n +-typesemiconductor layer 101 b. The dielectric film 104 (hereinafter, alsoreferred to as “insulator film”) covers a side surface of thesemiconductor layer 101 (a side surface of the first semiconductor layer101 a and a side surface of the second semiconductor layer 101 b). Also,the dielectric film 104 has an opening that is located on an uppersurface of the semiconductor layer 101 (first semiconductor layer 101a). The opening is provided between a part of the first semiconductorlayer 101 a and the metal layer 103 c of the Schottky electrode 103. Thedielectric film 104 may be extended so as to cover a part of the uppersurface of the semiconductor layer 101 (the first semiconductor layer101 a) in addition to cover a side surface of the semiconductor layer101. The dielectric film 104 of the semiconductor element of FIG. 1enables to improve a crystal defects at the end of the semiconductorlayer, to form a depletion layer more favorably. Also, the dielectricfilm 104 of the semiconductor element of FIG. 1 enables to improve arelaxation of electric s field that leads a more suppression of currentleakage. A preferred embodiment of the SBD is illustrated in FIG. 18, inwhich the porous layer 108 and the substrate 109 are provided.

FIG. 6 illustrates a main portion of a Schottly barrier diode (SBD) thatis the semiconductor element according to a preferred embodiment of thedisclosure. The SBD of FIG. 6 differs from the SBD of FIG. 1 in a pointthat a tapered region is provided on a side surface of the Schottkyelectrode 103. In the semiconductor element of FIG. 6, the outer end ofthe metal layer 103 b and/or the metal layer 103 c is located outer sidethan an outer end of the metal layer 103 a as the second metal layer.Therefore, it is possible to suppress leakage current more favorably.Also, a part of the metal layer 103 b and/or the metal layer 103 c thatis placed outer than the outer end of the metal layer 103 a has atapered region in which a film thickness is reducing toward the outsideof the semiconductor element. Therefore, the semiconductor element has amore enhanced withstand voltage.

Example of a material of the metal layer 103 a includes theabove-mentioned metals. In addition, examples of the materials of themetal layer 103 b and the metal layer 103 c include the above-describedmetals. A method of forming each layer of FIG. 1 is not particularlylimited unless it deviates from an object of the disclosure, and may bea known method. A method of forming each layer included in thesemiconductor device of FIG. 18 is not particularly limited unless itdeviates from an object of the disclosure, and may be a known method.Examples of the method of forming the each layer include a method inwhich, after a film is formed using a vacuum evaporation method, a CVDmethod, a sputtering method or other various coating techniques,patterning is conducted by photolithography. Also, examples of themethod of forming the each layer include a method in which patterning isconducted directly by using a printing technique and the like.

Hereinafter, a preferred manufacturing process of the SBD of FIG. 18will be described. The disclosure is not limited to these preferredmanufacturing methods. FIG. 2 (a) illustrates a multilayer body in whicha first semiconductor layer 101 a and a second semiconductor layer 101 bare provided on a crystal-growth substrate (a sapphire substrate) 110via a stress relaxation layer. The first semiconductor layer 101 a andthe second semiconductor layer 101 b are formed by above-mentioned mistCVD method. A multilayer structure of FIG. 2 (b) is obtained by forminga metal oxide layer (crystal) 102 a, a metal layer 102 b, and a metallayer 102 c as an Ohmic electrode. The metal oxide layer (crystal) 102a, a metal layer 102 b, and a metal layer 102 c are formed by theabove-mentioned dry method or the above-mentioned wet method. The firstsemiconductor layer 101 a is, for example, an n −-type semiconductorlayer. The second semiconductor layer 101 b is, for example, an n +-typesemiconductor layer 101 b. Further, a multilayer (c) is obtained bylaminating a substrate 109 on the multilayer structure of FIG. 2(b) viaa porous porous layer 108 that is made of a noble metal. Then, asillustrated in FIG. 3, the crystal-growth substrate 110 and the stressrelaxation layer 111 of the multilayer (c) are peeled off using a knownpeeling method, to obtain a multilayer structure (d). Then, asillustrated in FIG. 4, a multilayer structure (d) is obtained by etchingthe side surface of the semiconductor layer of the multilayer structure(d) to make tapered-shape. Next, obtaining a multilayer structure (f) byforming an insulating film 104 on the upper surface of the semiconductorlayer, other than an opening of of the semiconductor layer and thetapered side surface. Next, as illustrated in FIG. 5, a multilayerstructure (g) is obtained by forming a metal layers 103 a, 103 b and 103c as a Schottky electrode on the opening of the semiconductor layer. Themetal layers 103 a, 103 b and 103 c are formed by using theabove-mentioned dry method or the above-mentioned wet method. Thesemiconductor element obtained as described above has enhanced Ohmiccharacteristics. Also, a crystal defect of the end portion is improvedin the obtained semiconductor element. Therefore, a depletion layer isformed more favorably and the effect of a relaxation of electric fieldcan be obtained in the obtained semiconductor element. In addition, theobtained semiconductor element has a configuration that enables tosuppress more current leakage.

As an example of the disclosure, a semiconductor element of illustratedin FIG. 18 was produced based on the above-mentioned procedure.Materials used in the example 1 is as follows. α-(Ti_(x)Ga_(1-x))₂O₃film (in the formula, 0<X<1) was used as the metal oxide layer (crystal)102 a. Ti was used as the metal layer 102 b. Ni was used as the metallayer 102 c. Further, in the example 1 , an un-doped α--Ga₂O₃ was usedas the stress relaxation layer 111. Tin-doped α-Ga₂O₃ was used as thefirst semiconductor layer 101 a. Tin-doped α-Ga₂O₃ was used as thesecond semiconductor layer 101 b. Al was used as the metal layer 103 a.Ti was used as the metal layer 103 b. Co was used as the metal layer 103c. SiO₂ was used as the insulating film 104. A porous layer made of Agwas used as the porous layer 108. A electrically conductive substratecontaining Cu and Mo was used as the substrate 109. An exteriorphotograph of the obtained semiconductor element of the example 1 isillustrated in FIG. 8. Also, the observation result of thecross-sectional TEM at the analysis point of shown in FIG. 8 isillustrated in FIG. 9. The result of TEM-EDS analysis is illustrated inFIG. 10. As is apparent from FIGS. 9 and 10, it can be seen that thefilm of α-(Ti_(x)Ga_(1-x))₂O₃ (in the formula, 0.5<X<1) is well formed.Also, I-V measurement of the semiconductor element of the example 1 wasconducted. The results are illustrated in FIG. 7. As illustrated in FIG.7, it can be seen that the semiconductor element of the example 1 hasgood semiconductor properties.

As an example 2 , a semiconductor element was produced in the samemanner as example 1 except that a thickness of the metal oxide layer(crystal) 102 a was made to be thicker than a thickness of the metaloxide layer of the semiconductor element made in the example 1 . Thethickness of the metal oxide layer (crystal) 102 a was made to be equalto or more than 10 nm. A exterior photograph of the obtainedsemiconductor element of the example 2 is illustrated in FIG. 8. Theobservation result of the cross-sectional TEM at the analysis point ofFIG. 8 is illustrated in FIG. 9. The result of TEM-EDS analysis isillustrated in FIG. 11. As apparent from FIGS. 9 and 11, it can be seenthat the film of alpha-(Ti_(x)Ga_(1-x))₂O (in the 3 equation, 0.5<X<1)is well formed. Further, the I-V measurement of the semiconductorelement of the example 2 was conducted. The result of the I-Vmeasurement is illustrated in FIG. 7. As illustrated in FIG. 7, sincethe metal oxide layer (crystal) 102 a has a sufficient thickness, it canbe seen that the semiconductor element of the example 1 has moreenhanced semiconductor characteristics than the semiconductor element ofthe example 1.

Further, the semiconductor element is preferably a vertical device. Thesemiconductor device is especially useful for power devices. Examples ofthe semiconductor element includes, a diode (for example, a PN diode, aSchottky barrier diode, a junction barrier Schottky diode) and atransistor (for example, MOSFET or MESFET.). Among them, a diode ispreferable, and Schottky barrier diode (SBD) is more preferrable.

The semiconductor element according to an embodiment of the disclosure,in addition to the above description, may be used as a semiconductordevice. The semiconductor device is obtained by bonding thesemiconductor element to the lead frame, or a circuit board (a heatradiating substrate or the like. In particular, the semiconductorelement is preferably used for a power module, inverter, or a converter.Also, the semiconductor element is preferably used for a semiconductorsystem using a power supply device. A semiconductor device according toa preferred embodiment of the disclosure is illustrated in FIG. 15. Inthe semiconductor device of FIG. 15, both sides of a semiconductorelement 500, are bonded to lead frame or a board via solder 501. Here,the board is a circuit board or a heat dissipation board. With thisconfiguration, it is possible to obtain a semiconductor device havingenhanced heat dissipation. According to an embodiment of the disclosure,it is preferable that the periphery of the bonding member such as solderis sealed with resin.

The semiconductor device according to an embodiment of the disclosuremay be used as a power module, an inverter, and/or a converter incombination with a known structure. Also, a semiconductor deviceaccording to an embodiment of the disclosure may be used in asemiconductor system including a power source. In the power source, thesemiconductor device may be electrically connected, by a known structureand/or method, to a wiring pattern in the semiconductor system. FIG. 15is a schematic diagram illustrating an embodiment of a power sourcesystem. The power source system 170 of FIG. 15 includes two or morepower source devices 171 and 172, and a control circuit 173. Asillustrated in FIG. 16, the power source system 182 may be used for asystem device 180 in combination with an electric circuit 181. Anexample of a power source circuit of a power source device isillustrated in FIG. 17. The power source circuit of FIG. 17 includes apower circuit and a control circuit. A DC voltage is switched at highfrequencies by an inverter (configured with MOSFET A to D) to beconverted to AC, followed by insulation and transformation by atransformer. The voltage is then rectified by a rectification MOSFET andthen smoothed by a DCL (smoothing coils L1 and L2) and a capacitor tooutput a direct current voltage. At this point, the output voltage iscompared with a reference voltage by a voltage comparator 197 to controlthe inverter 192 and the rectification MOSFETs 194 by a PWM controlcircuit 196 to have a desired output voltage.

According to an embodiment of the disclosure, the semiconductor deviceis preferably a power card, and is more preferably the power cardincluding a first cooling device provided on a first side of asemiconductor layer including the crystalline oxide semiconductor via afirst insulating member and a second cooling device provided on a secondside of the semiconductor layer via a second insulating member. Here,the second side of the semiconductor layer is opposite to the first sideof the semiconductor layer. Further, it is most preferable that a firstheat dissipation layer is provided on the first side of thesemiconductor layer and a second heat dissipation layer is provided onthe second side of the semiconductor layer. According to the mostpreferable embodiment the first cooling device is provided on the firstheat dissipation layer via the first insulating member and the secondcooling device is provided on the second heat dissipation layer via thesecond insulating member. FIG. 16 illustrates a power card according toan embodiment of the present invention. The power card of FIG. 16 is adouble-sided cooled power card 201 including a refrigerant tube 202, aspacer 203, an insulating plate (an insulating spacer) 208, a resinsealing portion 209, a semiconductor chip 301 a, a metal heat transferplate (a protruding terminal portion) 302 b, a heat sink and anelectrode 303, a metal heat transfer plate (a protruding terminalportion) 303 b, a solder layer 304, a control electrode terminal 305,and a bonding wire 308. A refrigerant tube 202 has a number of flowpaths 222, in a thickness direction cross section thereof, that arepartitioned by a number of partition walls 221 extending in a flow pathdirection at certain intervals from each other. The power card accordingto the embodiment of the present invention enables to realize a higherheat dissipation and satisfy a higher reliability.

A semiconductor chip 301 a is bonded by a solder layer 304 on an innermain plane of the metal heat transfer plate 302 b. The metal heattransfer plate (protruding terminal portion) 302 b is bonded by a solderlayer 304 on a remaining area of the main plane of the semiconductorchip 301 a, so that a surface of an anode electrode and a surface of acathode electrode of a flywheel diode are connected in so-calledantiparallel, to a surface of a collector electrode and a surface of aemitter electrode of IGBT. Examples of material of the metal heattransfer plate (protruding terminal portions) 302 b and 303 b include Moand W. The metal heat transfer plate (protruding terminal portions) 302b and 303 b have a difference in thickness that absorbs a difference inthicknesses between the semiconductor chip 301 a and 301 b. Thisconfiguration enables an outer surface of the metal heat transfer plate302 to be planar.

A resin sealing portion 209 is made of, for example, epoxy resin. Sidesurfaces of the metal heat transfer plate 302 b and 303 b are covered tobe molded with the resin sealing portion 209, and the semiconductor chip301 a is molded with the resin sealing portion 209. However, outer mainplane of the heat transfer plates 302 b and 303 b, that is, contact heatreceiving surface of the heat transfer plates 302 b and 303 b iscompletely exposed. The metal heat transfer plate (protruding terminalportions) 302 b and 303 b protrudes to the right from the resin sealingportion 209, as illustrated in FIG.19. The control electrode terminal305 that is a lead frame terminal connects, for example, a gate(control) electrode surface of the semiconductor chip 301 a on whichIGBT is formed and the control electrode terminal 305.

The insulating plate 208 that is an insulating spacer, is made of, forexample, an aluminum nitride film, but may be other insulating films.The insulating plate 208 is completely covering the metal heat transferplates 302 b and 303 b and is in close contact with the metal heattransfer plates 302 b and 303 b, however, the insulating plate 208 andthe metal heat transfer plates 302 b and 303 b may be simply in contact.A high heat transfer material such as a silicon grease may be appliedbetween the insulating plate 208 and the metal heat transfer plates 302b and 303 b. Also, the insulating plate 208 and the metal heat transferplates 302 b and 303 b may be joined by using various methods. Further,an insulating layer may be formed as the insulating plate 208 by usingceramic spraying and the like. The insulating plate 208 may be bonded tothe metal heat transfer plate or may be joined or formed on therefrigerant tube.

INDUSTRIAL APPLICABILITY

The crystal and the semiconductor element according to the disclosurecan be used in various fields such as semiconductors (for example,compound semiconductor electronic devices), electronic components andelectric equipment components, optical and electronicphotography-related devices and industrial members, and especiallyuseful for power devices.

DESCRIPTION OF SYMBOLS

101 Semiconductor layer

101 first semiconductor layer

101 b second semiconductor layer

102 Ohmic electrode

102 metal oxide layer (crystal)

102 b metal layer

102 c metal layer

103 Schottky electrode

103 metal layer

103 b metal layer

103 metal layer

104 Insulating film

108 porous layer

109 substrate

110 crystal-growth substrate

170 power source system

171 power source device

172 power source device

173 control circuit

180 system device

181 electric circuit

182 power source system

192 inverter

193 transformer

194 MOSFET

195 DCL

196 PWM control circuit

197 voltage comparator

201 double-sided cooled power card

202 refrigerant tube

203 spacer

208 insulating plate (an insulating spacer)

209 resin sealing portion

221 partition wall

222 flow path

301 a semiconductor chip

302 b metal heat transfer plate (a protruding terminal portion)

303 heat sink and an electrode

303 b metal heat transfer plate (a protruding terminal portion)

304 solder layer

305 control electrode terminal

308 bonding wire

500 Semiconductor element

501 solder

502 lead frame, circuit board or heat dissipation board

What is claimed is:
 1. A crystal, comprising: a corundum structuredcrystalline oxide, the crystalline oxide including gallium and/orindium, and the crystalline oxide further including a metal of Group 4of the periodic table.
 2. The crystal according to claim 1, wherein themetal of Group 4 of the periodic table includes at least a metalselected from titanium, zirconium and hafnium.
 3. The crystal accordingto claim 1, wherein the metal of Group 4 of the periodic table istitanium.
 4. The crystal according to claim 1, wherein the crystallineoxide contains gallium.
 5. The crystal according to claim 1, wherein thecrystal has a shape of a film.
 6. The crystal according to claim 1,wherein the crystal has an electrical conductivity.
 7. A semiconductorelement, comprising: the crystal according to claim
 1. 8. Asemiconductor element, comprising: a semiconductor layer; an electrodethat is arranged on the semiconductor layer, the electrode includes thecrystal according to claim
 6. 9. The semiconductor element according toclaim 8, wherein the semiconductor layer includes a crystalline oxidesemiconductor as a major component.
 10. The semiconductor elementaccording to claim 9, wherein the crystalline oxide semiconductor has acorundum structure.
 11. The semiconductor element according to claim 9,wherein the crystalline oxide semiconductor contains at least one ormore metals selected from aluminum, gallium and indium.
 12. Thesemiconductor element according to claim 7, wherein the semiconductorelement is a vertical device.
 13. The semiconductor element according toclaim 7, wherein the semiconductor element is a power device.
 14. Asemiconductor device, comprising: the semiconductor element according toclaim 7; a board; and a jointing material, and the semiconductor elementthat is bonded with the board by using the jointing material, the boardis a circuit board or a heat dissipation board.
 15. The semiconductordevice according to claim 14, wherein the semiconductor device is apower module, an inverter, or a converter.
 16. The semiconductor deviceaccording to claim 14, wherein the semiconductor device is a power card.17. A semiconductor system, comprising: the semiconductor elementaccording to claim 7.